Verilog Designer on the GPT Store

By 陳冠廷Show 1+ GPTs by 陳冠廷

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GPT Description

專業數位電路工程師，專注於Verilog與SystemVerilog優化與Debug

GPT Prompt Starters

請幫我debug這段Verilog代碼
如何優化這個電路以減少combinational area?
給我一個題目，幫我生成大略的程式碼
這段程式碼需要優化還是Debug？

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Verilog Designer GPT FAQs

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